1. Field of the Invention
The invention relates to an output circuit, particularly to an output circuit capable of taking out three states of an output terminal, namely, a power supply voltage level, ground voltage level and a high impedance state.
2. Description of the Related Art
In a semiconductor integrated circuit, there is provided an output circuit for driving a load of an external circuit that operates in response to an output signal from the semiconductor integrated circuit and a wiring having a large load capacitor in the semiconductor integrated circuit. Accordingly, transistors constituting the output circuit have a large driving capacity compared with general transistors constituting the semiconductor integrated circuit.
An output stage of the output circuit is generally composed of two transistors that are serially connected with each other between a power supply voltage supply terminal (referred to as power voltage supply terminal) and a ground voltage supply terminal, wherein the connecting point of these transistors forms an output terminal. With such a construction, there occurs a timing when these two transistors are conducted, thereby producing a feedthrough current. Since the output circuit employs transistors having such a large driving capacity, the feedthrough current becomes large. The feedthrough current in such an output circuit is to negligible in the semiconductor integrated circuit requiring a low consumption power. As a method of reducing the feedthrough current of the output circuit is disclosed, for example, in the following literature.
Name of literature: Japanese Patent publication No. 8-84057
The aforementioned literature employs a NAND gate or a NOR gate wherein a timing when one or both signals having complementary voltage levels are inputted to the NAND gate or the NOR gate in delayed by an inverter to render both transistors nonconductive, then to render one transistor conductive. With such a construction, two transistors constituting an output stage of the output circuit does not become conductive at the same time.
In the method disclosed in the aforementioned literature, an output signal of the output stage always generates a high impedance state for the time corresponding to the delay time by the inverter. Accordingly, even in a timing when feedthrough current is not produced depending on two input signals inputted to the output circuit, the high impedance state is always generated for a given time. Accordingly, high speed responsivity of the output circuit is to always satisfied.
As viewed from input terminals of the output circuit to which signals are inputted, there occurs delay in the operation of the output stage by the time involved in passing through the NAND gate or NOR gate in addition to the delay by the inverter. In this case, if a noise is generated in the signal inputted to the output circuit, the state of the output signal from the output circuit is stabilized after it is temporarily rendered to a high impedance state via the inverter, the NAND gate or NOR gate.
It is an object of the invention to solve the aforementioned problems and provide an output circuit capable of reducing a feedthrough current in the output stage of the output circuit without deteriorating the high speed responsivity.
It is another object of the invention to provide an output circuit capable of reducing the increase of the number of elements as much as possible, thereby achieving the above object.
It is still another object of the invention to provide an output circuit capable of achieving the above object even if a noise is generated in signals to be inputted thereto.